✅ UNIT 4 — Microprocessor Basics, Instruction Cycle, Pipelining & Hazards

 This unit connects digital electronics to how a CPU actually works internally.

⭐ 4.1 What is a Microprocessor?

A microprocessor is the brain of the computer, an IC that performs:

• Arithmetic operations (ALU)

• Logical operations

• Control (via CU)

• Data transfer

Examples:

• 8085 (8-bit, classic for exams)

• 8086 (16-bit)

• i3, i5, i7 (modern CPUs)

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⭐ 4.2 Basic Microprocessor Architecture

Major Components:

1️⃣ ALU (Arithmetic Logic Unit)

Performs:

• Add, Subtract

• AND, OR, NOT

• Compare

2️⃣ Control Unit (CU)

• Controls timing

• Fetch, Decode, Execute instructions

• Sends control signals to memory and I/O

3️⃣ Registers

High-speed small storage inside CPU:

• Accumulator (A)

• General registers (B, C, D, E, H, L)

• Program Counter (PC)

• Stack Pointer (SP)

• Flag Register (Z, S, CY, P, AC flags)

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⭐ 4.3 Instruction Cycle

Every instruction executes in three steps:

1️⃣ Fetch Cycle

• PC → Address Bus

• Memory → Instruction → CPU

• PC = PC + 1

2️⃣ Decode Cycle

• Instruction decoded by Control Unit

• Identifies required operation

3️⃣ Execute Cycle

• ALU performs operation

• Result stored in Register/Memory

• Flags updated

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⭐ 4.4 Machine Cycle & T-States

Machine Cycle:

A part of instruction cycle (memory read, memory write, I/O read, etc.)

T-States:

Each machine cycle is divided into clock cycles.

Example (8085):

• Memory Read Cycle = 3 T-states

• Memory Write Cycle = 3 T-states

• Opcode Fetch Cycle = 4 T-states

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⭐ 4.5 Addressing Modes

Defines how data is accessed.

Mode	Example	Meaning
Immediate	MVI A, 05H	Data is inside instruction
Direct	LDA 2050H	Access memory address directly
Register	MOV A, B	Data is in register
Indirect	LDAX B	Address is held in register pair
Implicit	CMA	Operand is fixed

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⭐ 4.6 Instruction Format

8085 uses:

• 1-byte instructions

• 2-byte instructions

• 3-byte instructions

Example:
MOV A, B → 1 byte
MVI A, 32H → 2 bytes
LDA 2050H → 3 bytes

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⭐ 4.7 Interrupts

Interrupt = CPU’s attention signal.

Types:

1. Hardware – RST 7.5, RST 6.5, RST 5.5, INTR

2. Software – RST instruction

3. Maskable / Non-maskable

4. Vectored / Non-vectored

Example:

• TRAP → Non-maskable, vectored

• RST 7.5 → Maskable, vectored

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⭐ 4.8 Pipelining

Modern CPUs use pipelines to speed up execution.

Typical stages (RISC pipeline):

1. IF – Instruction Fetch

2. ID – Instruction Decode

3. EX – Execute

4. MEM – Memory Access

5. WB – Write Back

Why pipelining is fast?

Because multiple instructions execute in parallel.

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⭐ 4.9 Types of Pipelines

• Superpipelining
  (More pipeline stages)

• Superscalar Pipeline
  (More than one instruction issued per cycle)

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⭐ 4.10 Pipeline Hazards

These are problems that slow down pipelined execution.

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1️⃣ Data Hazard

Occurs when one instruction depends on the result of the previous one.

Example:

I1: ADD R1, R2, R3  
I2: SUB R4, R1, R5   ← depends on R1  

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2️⃣ Control Hazard

Occurs in branching.

Example:

BEQ LABEL

Branch decision unknown → pipeline stalls.

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3️⃣ Structural Hazard

Two instructions need the same hardware resource at the same time.

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Solutions to hazards

• Forwarding / Bypassing

• Pipeline Stalling

• Branch Prediction

• Separate instruction & data memory